C8051F80X_14 Datasheet, PDF (110/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 18.6. EIP2: Extended Interrupt Priority 2
Bit
7
Name ^Reserved
Type
R
Reset
0
6
Reserved
R
0
5
Reserved
R
0
4
Reserved
R
0
3
Reserved
R
0
2
Reserved
R
0
1
PSCGRT
R/W
0
0
PSCCPT
R/W
0
SFR Address = 0xF4
Bit Name
Function
7:2 Reserved
1 PSCGRT Capacitive Sense Greater Than Comparator Priority Control.
This bit sets the priority of the Capacitive Sense Greater Than Comparator interrupt.
0: CS0 Greater Than Comparator interrupt set to low priority level.
1: CS0 Greater Than Comparator set to high priority level.
0 PSCCPT Capacitive Sense Conversion Complete Priority Control.
This bit sets the priority of the Capacitive Sense Conversion Complete interrupt.
0: CS0 Conversion Complete set to low priority level.
1: CS0 Conversion Complete set to high priority level.
110
Rev. 1.0