C8051F80X_14 Datasheet, PDF (131/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
22.2. Programmable Internal High-Frequency (H-F) Oscillator
All C8051F80x-83x devices include a programmable internal high-frequency oscillator that defaults as the
system clock after a system reset. The internal oscillator period can be adjusted via the OSCICL register
as defined by SFR Definition 22.2.
On C8051F80x-83x devices, OSCICL is factory calibrated to obtain a 24.5 MHz base frequency.
The internal oscillator output frequency may be divided by 1, 2, 4, or 8, as defined by the IFCN bits in reg-
ister OSCICN. The divide value defaults to 8 following a reset.
The precision oscillator supports a spread spectrum mode which modulates the output frequency in order
to reduce the EMI generated by the system. When enabled (SSE = 1), the oscillator output frequency is
modulated by a stepped triangle wave whose frequency is equal to the oscillator frequency divided by 384
(63.8 kHz using the factory calibration). The maximum deviation from the center frequency is ±0.75%. The
output frequency updates occur every 32 cycles and the step size is typically 0.25% of the center fre-
quency.
SFR Definition 22.2. OSCICL: Internal H-F Oscillator Calibration
Bit
Name
Type
Reset
7
Varies
6
Varies
5
Varies
4
3
OSCICL[6:0]
R/W
Varies
Varies
2
Varies
1
Varies
0
Varies
SFR Address = 0xB3
Bit Name
Function
6:0 OSCICL[7:0] Internal Oscillator Calibration Bits.
These bits determine the internal oscillator period. When set to 00000000b, the H-F
oscillator operates at its fastest setting. When set to 11111111b, the H-F oscillator
operates at its slowest setting. The reset value is factory calibrated to generate an
internal oscillator frequency of 24.5 MHz.
Rev. 1.0
131