C8051F80X_14 Datasheet, PDF (101/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
Table 17.2. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
SBUF0
SCON0
SMB0ADM
SMB0ADR
SMB0CF
Address
Description
0x99 UART0 Data Buffer
0x98 UART0 Control
0xD6 SMBus Slave Address mask
0xD7 SMBus Slave Address
0xC1 SMBus Configuration
SMB0CN
SMB0DAT
SP
SPI0CFG
SPI0CKR
SPI0CN
0xC0
0xC2
0x81
0xA1
0xA2
0xF8
SMBus Control
SMBus Data
Stack Pointer
SPI0 Configuration
SPI0 Clock Rate Control
SPI0 Control
SPI0DAT
0xA3
TCON
0x88
TH0
0x8C
TH1
0x8D
TL0
0x8A
TL1
0x8B
TMOD
0x89
TMR2CN
0xC8
TMR2H
0xCD
TMR2L
0xCC
TMR2RLH
0xCB
TMR2RLL
0xCA
VDM0CN
0xFF
XBR0
0xE1
XBR1
0xE2
All other SFR Locations
SPI0 Data
Timer/Counter Control
Timer/Counter 0 High
Timer/Counter 1 High
Timer/Counter 0 Low
Timer/Counter 1 Low
Timer/Counter Mode
Timer/Counter 2 Control
Timer/Counter 2 High
Timer/Counter 2 Low
Timer/Counter 2 Reload High
Timer/Counter 2 Reload Low
VDD Monitor Control
Port I/O Crossbar Control 0
Port I/O Crossbar Control 1
Reserved
Page
207
206
191
191
186
188
192
89
174
176
175
176
215
218
218
217
217
216
222
224
224
223
223
126
148
149
Rev. 1.0
101