C8051F80X_14 Datasheet, PDF (50/251 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F80x-83x
SFR Definition 8.1. ADC0CF: ADC0 Configuration
Bit
7
Name
Type
Reset
1
6
5
4
AD0SC[4:0]
R/W
1
1
1
3
2
1
0
AD0LJST AD08BE AMP0GN0
R/W
R/W
R/W
1
0
0
1
SFR Address = 0xBC
Bit Name
Function
7:3 AD0SC[4:0] _{ADC0 SAR Conversion Clock Period Bits.}
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4–0. SAR Conversion clock
requirements are given in the ADC specification table.
AD0SC = -S---Y----S----C----L---K--- – 1
CLK_SAR
2 AD0LJST _{ADC0 Left Justify Select.}
0: Data in ADC0H:ADC0L registers are right-justified.
1: Data in ADC0H:ADC0L registers are left-justified.
Note: The AD0LJST bit is only valid for 10-bit mode (AD08BE = 0).
1 AD08BE _{8-Bit Mode Enable.}
0: ADC operates in 10-bit mode (normal).
1: ADC operates in 8-bit mode.
Note: When AD08BE is set to 1, the AD0LJST bit is ignored.
0 AMP0GN0 _{ADC Gain Control Bit.}
0: Gain = 0.5
1: Gain = 1
50
Rev. 1.0