C8051F58X Datasheet, PDF (90/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
If the internal voltage regulator is not used, the VREGIN input should be tied to VDD, as shown in
Figure 10.2.
V_REGIN
V_DD
4.7 µF
V_DD
.1 µF
Figure 10.2. External Capacitors for Voltage Regulator
Input/Output—Regulator Disabled
SFR Definition 10.1. REG0CN: Regulator Control
Bit
7
6
5
4
3
2
Name REGDIS Reserved
REG0MD
Type R/W
R/W
R
R/W
R
R
Reset
0
1
0
1
0
0
SFR Address = 0xC9; SFR Page = 0x00
Bit
Name
Function
7
REGDIS Voltage Regulator Disable Bit.
0: Voltage Regulator Enabled
1: Voltage Regulator Disabled
6 Reserved Read = 1b; Must Write 1b.
5
Unused Read = 0b; Write = Don’t Care.
4 REG0MD Voltage Regulator Mode Select Bit.
0: Voltage Regulator Output is 2.1V.
1: Voltage Regulator Output is 2.6V.
3:1 Unused Read = 000b. Write = Don’t Care.
0 DROPOUT Voltage Regulator Dropout Indicator.
0: Voltage Regulator is not in dropout
1: Voltage Regulator is in or near dropout.
1
0
DROPOUT
R
R
0
0
90
Rev. 1.2