C8051F58X Datasheet, PDF (33/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
Figure 4.2. QFP-48 Landing Diagram
Table 4.2. QFP-48 Landing Diagram Dimensions
Dimension
C1
C2
E
Min
Max
8.30
8.40
8.30
8.40
0.50 BSC
Dimension
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
Min
0.20
1.40
Max
0.30
1.50
Solder Mask Design
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the
metal pad is to be 60 m minimum, all the way around the pad.
Stencil Design
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure
good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
Card Assembly
7. A No-Clean, Type-3 solder paste is recommended.
8. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
Components.
Rev. 1.2
33