C8051F58X Datasheet, PDF (133/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
SFR Definition 14.4. EIP1: Extended Interrupt Priority 1
Bit
Name
Type
Reset
7
PLIN0
R/W
0
6
PT3
R/W
0
5
PCP1
R/W
0
4
PCP0
R/W
0
3
PPCA0
R/W
0
2
PADC0
R/W
0
1
PWADC0
R/W
0
SFR Address = 0xF6; SFR Page = All Pages
Bit Name
Function
7 PLIN0 LIN0 Interrupt Priority Control.
This bit sets the priority of the LIN0 interrupt.
0: LIN0 interrupts set to low priority level.
1: LIN0 interrupts set to high priority level.
6
PT3 Timer 3 Interrupt Priority Control.
This bit sets the priority of the Timer 3 interrupt.
0: Timer 3 interrupts set to low priority level.
1: Timer 3 interrupts set to high priority level.
5 PCP1 Comparator0 (CP1) Interrupt Priority Control.
This bit sets the priority of the CP1 interrupt.
0: CP1 interrupt set to low priority level.
1: CP1 interrupt set to high priority level.
4 PCP0 Comparator0 (CP0) Interrupt Priority Control.
This bit sets the priority of the CP0 interrupt.
0: CP0 interrupt set to low priority level.
1: CP0 interrupt set to high priority level.
3 PPCA0 Programmable Counter Array (PCA0) Interrupt Priority Control.
This bit sets the priority of the PCA0 interrupt.
0: PCA0 interrupt set to low priority level.
1: PCA0 interrupt set to high priority level.
2 PADC0 ADC0 Conversion Complete Interrupt Priority Control.
This bit sets the priority of the ADC0 Conversion Complete interrupt.
0: ADC0 Conversion Complete interrupt set to low priority level.
1: ADC0 Conversion Complete interrupt set to high priority level.
1 PWADC0 ADC0 Window Comparator Interrupt Priority Control.
This bit sets the priority of the ADC0 Window interrupt.
0: ADC0 Window interrupt set to low priority level.
1: ADC0 Window interrupt set to high priority level.
0 PSMB0 SMBus (SMB0) Interrupt Priority Control.
This bit sets the priority of the SMB0 interrupt.
0: SMB0 interrupt set to low priority level.
1: SMB0 interrupt set to high priority level.
0
PSMB0
R/W
0
Rev. 1.2
133