C8051F58X Datasheet, PDF (192/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. CAN0 pin assignments are fixed to P0.6 for CAN_TX and P0.7 for
CAN_RX. Standard Port I/Os appear contiguously after the prioritized functions have been assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
As an example configuration, if CAN0, SPI0 in 4-wire mode, and PCA0 Modules 0, 1, and 2, 6, and 7 are
enabled on the crossbar with P0.1, P0.2, and P0.5 skipped, the registers should be set as follows: XBR0 =
0x06 (CAN0 and SPI0 enabled), XBR1 = 0x0C (PCA0 modules 0, 1, and 2 enabled), XBR2 = 0x40 (Cross-
bar enabled), XBR3 = 0x02 (PCA1 modules 6 and 7) and P0SKIP = 0x26 (P0.1, P0.2, and P0.5 skipped).
The resulting crossbar would look as shown in Figure 20.4.
Port
P0
P1
P2
P3
P4
Special
Function
Signals
P3.1-P3.7, P4.0 only P4.1-P4.7 only
available on the 48-pin available on the 48-
and 40-pin packages
pin packages
PIN I/O 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
UART0_TX
UART0_RX
CAN_TX
CAN_RX
SCK
MISO
MOSI
NSS
SDA
*NSS Is only pinned out in 4-wire SPI Mode
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
LIN_TX
LIN_RX
UART1_TX
UART1_RX
CP2
CP2A
CEX6
CEX7
CEX8
CEX9
CEX10
CEX11
ECI1
T4
T4EX
T5
T5EX
01100100000000000000000000000000
P0SKIP[0:7]
P1SKIP[0:7]
P2SKIP[0:7]
P3SKIP[0:7]
Figure 20.4. Crossbar Priority Decoder in Example Configuration
192
Rev. 1.2