C8051F58X Datasheet, PDF (117/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
Table 13.1. Special Function Register (SFR) Memory Map for Pages 0x00, 0x10, and 0x0F
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
F8 00 SPI0CN
10
0F
PCA0L
PCA1L
SN0
PCA0H
PCA1H
SN1
PCA0CPL0 PCA0CPH0 PCACPL4 PCACPH4
PCA1CPL6 PCA1CPH6 PCA1CPL10 PCA1CPH10
SN2
SN3
VDM0CN
F0 00 B
P0MAT
10 ^{(All Pages)}
0F
P0MDIN
P0MASK
P1MDIN
P1MAT
P2MDIN
P1MASK
P3MDIN
PSBANK
(All Pages)
EIP1
EIP1
EIP2
EIP2
E8 00 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPL3
10
PCA1CPL7 PCA1CPH7 PCA1CPL8 PCA1CPH8 PCA1CPL9 PCA1CPL9
RSTSRC
0F
E0 00 ACC
10 ^{(All Pages)}
0F
XBR0
XBR1 CCH0CN IT01CF
EIE1
EIE2
(All Pages) (All Pages)
D8 00 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3P PCA0CPM4P PCA0CPM5
10 ^{PCA1CN PCA1MD PCA1CPM6 PCA1CPM7 PCA1CPM8 CA1CPM9 CA1CPM10 PCA1CPM11}
0F
PCA0PWM
D0 00 PSW REF0CN
10 ^{(All Pages)}
0F
LIN0DATA LIN0ADDR
P0SKIP
P1SKIP
P2SKIP
P3SKIP
C8 00 TMR2CN
10 ^TMR4CN
0F
REG0CN TMR2RLL TMR2RLH
TMR4CF TMR4CAPL TMR4CAPH
LIN0CF
TMR2L
TMR4L
TMR2H
TMR4H
PCA0CPL5 PCA0CPH5
PCA1CPL11 PCA1CPH11
C0 00 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH
10
0F
XBR3
XBR2
B8 00 IP
10 ^{(All Pages)}
ADC0TK ADC0MX ADC0CF
ADC0L
ADC0H
0F
B0 00 P3
10 ^{(All Pages)}
0F
P2MAT
P2MASK
EMI0CF
P4
FLSCL
FLKEY
(All Pages) (All Pages) (All Pages)
A8 00 IE
SMOD0
10 ^{(All Pages)}
0F
EMI0CN
EMI0TC SBCON0
SBRLL0
SBRLH0
P3MAT
P3MASK
P3MDOUT P4MDOUT
A0 00 P2 SPI0CFG
10 ^{(All Pages)}
0F
OSCICN
SPI0CKR
OSCICRS
SPI0DAT
P0MDOUT
P1MDOUT
P2MDOUT
SFRPAGE
(All Pages)
98 00 SCON0
10 ^SCON1
0F
SBUF0
SBUF1
CPT0CN CPT0MD
CPT2CN CPT2MD
CPT0MX
CPT2MX
CPT1CN
CPT1MD
OSCIFIN
CPT1MX
OSCXCN
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
(bit addressable)
Rev. 1.2
117