C8051F58X Datasheet, PDF(46/356 Page) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

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C8051F58X Datasheet, PDF (46/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

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C8051F58x/F59x

Figure 5.1. Maximum System Clock Frequency vs. VDD Voltage

Note: With system clock frequencies greater than 25 MHz, the VDD monitor level should be set to the high threshold

(VDMLVL = 1b in SFR VDM0CN) to prevent undefined CPU operation. The high threshold should only be used

with an external regulator powering VDD directly. See Figure 10.2 on page 90 for the recommended power

supply connections.

46

Rev. 1.2

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