C8051F58X Datasheet, PDF (9/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
List of Figures
Figure 1.1. C8051F580/1/4/5 Block Diagram .......................................................... 19
Figure 1.2. C8051F588/9-F590/1 Block Diagram .................................................... 20
Figure 1.3. C8051F582/3/6/7 Block Diagram .......................................................... 21
Figure 3.1. QFP-48 Pinout Diagram (Top View) ...................................................... 27
Figure 3.2. QFN-48 Pinout Diagram (Top View) ..................................................... 28
Figure 3.3. QFN-40 Pinout Diagram (Top View) ..................................................... 29
Figure 3.4. QFP-32 Pinout Diagram (Top View) ...................................................... 30
Figure 3.5. QFN-32 Pinout Diagram (Top View) ..................................................... 31
Figure 4.1. QFP-48 Package Drawing ..................................................................... 32
Figure 4.2. QFP-48 Landing Diagram ..................................................................... 33
Figure 4.3. QFN-48 Package Drawing .................................................................... 34
Figure 4.4. QFN-48 Landing Diagram ..................................................................... 35
Figure 4.5. Typical QFN-40 Package Drawing ........................................................ 36
Figure 4.6. QFN-40 Landing Diagram ..................................................................... 37
Figure 4.7. QFP-32 Package Drawing ..................................................................... 38
Figure 4.8. QFP-32 Package Drawing ..................................................................... 39
Figure 4.9. QFN-32 Package Drawing .................................................................... 40
Figure 4.10. QFN-32 Package Drawing .................................................................. 41
Figure 5.1. Maximum System Clock Frequency vs. VDD Voltage .......................... 46
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 54
Figure 6.2. ADC0 Tracking Modes .......................................................................... 56
Figure 6.3. 12-Bit ADC Tracking Mode Example ..................................................... 57
Figure 6.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4 ............. 58
Figure 6.5. ADC0 Equivalent Input Circuit ............................................................... 60
Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 71
Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 71
Figure 6.8. ADC0 Multiplexer Block Diagram .......................................................... 72
Figure 7.1. Temperature Sensor Transfer Function ................................................ 74
Figure 8.1. Voltage Reference Functional Block Diagram ....................................... 75
Figure 9.1. Comparator Functional Block Diagram ................................................. 77
Figure 9.2. Comparator Hysteresis Plot .................................................................. 78
Figure 9.3. Comparator Input Multiplexer Block Diagram ........................................ 85
Figure 10.1. External Capacitors for Voltage Regulator Input/Output—
Regulator Enabled ............................................................................... 89
Figure 10.2. External Capacitors for Voltage Regulator
Input/Output—Regulator Disabled ...................................................... 90
Figure 11.1. CIP-51 Block Diagram ......................................................................... 92
Figure 12.1. C8051F58x/F59x Memory Map ......................................................... 102
Figure 12.2. Flash Program Memory Map ............................................................. 103
Figure 12.3. Address Memory Map for Instruction Fetches ................................... 103
Figure 13.1. SFR Page Stack ................................................................................ 107
Figure 13.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT . 108
Figure 13.3. SFR Page Stack After CAN0 Interrupt Occurs .................................. 109
Rev. 1.2
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