C8051F58X Datasheet, PDF (102/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
12. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization is shown in
Figure 12.1
PROGRAM/DATA MEMORY
(FLASH)
0x1FFFF
0x1FC00
0x1FBFF
C8051F580/1/2/3/8/9
RESERVED
0xFF
0x80
0x7F
128 kB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x30
0x2F
0x20
0x1F
0x00
DATA MEMORY (RAM)
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing
Only)
Special Function
Register's
(Direct Addressing Only)
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
Registers
Lower 128 RAM
(Direct and Indirect
Addressing)
0x00000
C8051F584/5/6/7-F590/1
0x17FFF
96 kB FLASH
(In-System
Programmable in 512
Byte Sectors)
0x00000
EXTERNAL DATA ADDRESS SPACE
0xFFFF
Same 8192 bytes as
from 0x0000 to 0x1FFF,
wrapped on 8192-byte
boundaries
0x2000
0x1FFF
0x0000
XRAM
8K Bytes
(accessable using
MOVX instruction)
Figure 12.1. C8051F58x/F59x Memory Map
12.1. Program Memory
The C8051F580/1/2/3/8/9 devices have a 128 kB program memory space and the C8051F584/5/6/7-
F590/1 devices have 96 kB program memory space. The MCU implements this program memory space as
in-system re-programmable Flash memory in either four or three 32 kB code banks. A common code bank
(Bank 0) of 32 kB is always accessible from addresses 0x0000 to 0x7FFF. The three or two upper code
banks (Bank 1, Bank 2, and Bank 3) are each mapped to addresses 0x8000 to 0xFFFF, depending on the
selection of bits in the PSBANK register, as described in SFR Definition 12.1.
102
Rev. 1.2