C8051F58X Datasheet, PDF (22/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
2. Ordering Information
The following features are common to all devices in this family:
 50 MHz system clock and 50 MIPS throughput (peak)
 8448 bytes of RAM (256 internal bytes and 8192 XRAM bytes
 SMBus/I²C, Enhanced SPI, Two UARTs
 Six Timers
 12 Programmable Counter Array channels
 12-bit, 200 ksps ADC
 Internal 24 MHz oscillator
 Internal Voltage Regulator
 Internal Voltage Reference and Temperature Sensor
 Three Analog Comparators
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Table 2.1 shows the feature that differentiate the devices in this family.
22
Rev. 1.2