C8051F58X Datasheet, PDF (345/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
SFR Definition 29.3. PCA1PWM: PCA1 PWM Configuration
Bit
7
6
5
4
3
2
1
0
Name ^{ARSEL1 ECOV1 COVF1}
CLSEL1[1:0]
Type ^R/W
R/W
R/W
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xDA; SFR Page = 0x0F
Bit
Name
Function
7 ARSEL1 Auto-Reload Register Select.
This bit selects whether to read and write the normal PCA1 capture/compare regis-
ters (PCA1CPn), or the Auto-Reload registers at the same SFR addresses. This
function is used to define the reload value for 9, 10, and 11-bit PWM modes. In all
other modes, the Auto-Reload registers have no function.
0: Read/Write Capture/Compare Registers at PCA1CPHn and PCA1CPLn.
1: Read/Write Auto-Reload Registers at PCA1CPHn and PCA1CPLn.
6
ECOV1 Cycle Overflow Interrupt Enable.
This bit sets the masking of the Cycle Overflow Flag (COVF1) interrupt.
0: COVF1 will not generate PCA1 interrupts.
1: A PCA1 interrupt will be generated when COVF1 is set.
5
COVF1 Cycle Overflow Flag.
This bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main PCA1 coun-
ter (PCA1). The specific bit used for this flag depends on the setting of the Cycle
Length Select bits. The bit can be set by hardware or software, but must be cleared
by software.
0: No overflow has occurred since the last time this bit was cleared.
1: An overflow has occurred since the last time this bit was cleared.
4:2 Unused Read = 000b; Write = Don’t care.
1:0 CLSEL1[1:0] Cycle Length Select.
When 16-bit PWM mode is not selected, these bits select the length of the PWM
cycle, between 8, 9, 10, or 11 bits. This affects all channels configured for PWM
which are not using 16-bit PWM mode. These bits are ignored for individual chan-
nels configured to16-bit PWM mode.
00: 8 bits.
01: 9 bits.
10: 10 bits.
11: 11 bits.
Rev. 1.2
345