C8051F58X Datasheet, PDF (343/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
29.4. Register Descriptions for PCA1
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 29.1. PCA1CN: PCA1 Control
Bit
7
Name ^CF1
Type ^R/W
Reset
0
6
CR1
R/W
0
5
CCF6
R/W
0
4
CCF7
R/W
0
3
CCF8
R/W
0
2
CCF9
R/W
0
1
CCF10
R/W
0
0
CCF11
R/W
0
SFR Address = 0xD8; Bit-Addressable; SFR Page = 0x10
Bit Name
Function
7
CF1 PCA1 Counter/Timer Overflow Flag.
Set by hardware when the PCA1 Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF1) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA1 interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
6
CR1 PCA1 Counter/Timer Run Control.
This bit enables/disables the PCA1 Counter/Timer.
0: PCA1 Counter/Timer disabled.
1: PCA1 Counter/Timer enabled.
5 CCF11 PCA1 Module 11 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF11 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
4 CCF10 PCA1 Module 10 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF10 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
3 CCF9 PCA1 Module 9 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF9 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
2 CCF8 PCA1 Module 8 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF8 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
1 CCF7 PCA1 Module 7 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF7 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
0 CCF6 PCA1 Module 6 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF6 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA1 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
Rev. 1.2
343