C8051F58X Datasheet, PDF (152/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
17.2. Power-Fail Reset/V_DD Monitor
When a power-down transition or power irregularity causes V_DD to drop below V_RST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 17.2). When V_DD returns
to a level above V_RST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if V_DD dropped below
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The V_DD
monitor is enabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the V_DD monitor is disabled by code and a software reset is performed, the
V_DD monitor will still be disabled after the reset. To protect the integrity of Flash contents, the V_DD
monitor must be enabled to the higher setting (VDMLVL = 1) and selected as a reset source if soft-
ware contains routines which erase or write Flash memory. If the V_DD monitor is not enabled and
set to the high level, any erase or write performed on Flash memory will cause a Flash Error device
reset.
Important Note: If the V_DD monitor is being turned on from a disabled state, it should be enabled before it
is selected as a reset source. Selecting the V_DD monitor as a reset source before it is enabled and stabi-
lized may cause a system reset. In some applications, this reset may be undesirable. If this is not desirable
in the application, a delay should be introduced between enabling the monitor and selecting it as a reset
source. The procedure for enabling the V_DD monitor and configuring it as a reset source from a disabled
state is as follows:
1. Enable the V_DD monitor (VDMEN bit in VDM0CN = 1).
2. If necessary, wait for the V_DD monitor to stabilize (see Table 5.4 for the V_DD Monitor turn-on time).
Note: This delay should be omitted if software contains routines that erase or write Flash
memory.
3. Select the V_DD monitor as a reset source (PORSF bit in RSTSRC = 1).
See Figure 17.2 for V_DD monitor timing; note that the power-on-reset delay is not incurred after a V_DD
monitor reset. See Table 5.4 for complete electrical characteristics of the V_DD monitor.
Note: The output of the internal voltage regulator is calibrated by the MCU immediately after any reset event. The
output of the un-calibrated internal regulator could be below the high threshold setting of the VDD Monitor. If
this is the case and the VDD Monitor is set to the high threshold setting and if the MCU receives a non-power
on reset (POR), the MCU will remain in reset until a POR occurs (i.e., V_DD Monitor will keep the device in reset).
A POR will force the VDD Monitor to the low threshold setting which is guaranteed to be below the un-
calibrated output of the internal regulator. The device will then exit reset and resume normal operation. It is for
this reason Silicon Labs strongly recommends that the V_DD Monitor is always left in the low threshold setting
(i.e. default value upon POR).
When programming the Flash in-system, the V_DD Monitor must be set to the high threshold setting. For the
highest system reliability, the time the V_DD Monitor is set to the high threshold setting should be minimized
(e.g., setting the V_DD Monitor to the high threshold setting just before the Flash write operation and then
changing it back to the low threshold setting immediately after the Flash write operation).
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