C8051F58X Datasheet, PDF (325/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
28.5. Register Descriptions for PCA0
Following are detailed descriptions of the special function registers related to the operation of the PCA.
SFR Definition 28.1. PCA0CN: PCA0 Control
Bit
7
Name
CF
Type ^R/W
Reset
0
6
5
4
3
2
1
0
CR
CCF5
CCF4
CCF3
CCF2
CCF1
CCF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
SFR Address = 0xD8; Bit-Addressable; SFR Page = 0x00
Bit Name
Function
7
CF PCA0 Counter/Timer Overflow Flag.
Set by hardware when the PCA0 Counter/Timer overflows from 0xFFFF to 0x0000.
When the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the
CPU to vector to the PCA0 interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
6
CR PCA0 Counter/Timer Run Control.
This bit enables/disables the PCA0 Counter/Timer.
0: PCA0 Counter/Timer disabled.
1: PCA0 Counter/Timer enabled.
5 CCF5 PCA0 Module 5 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF5 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA0 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
4 CCF4 PCA0 Module 4 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF4 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA0 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
3 CCF3 PCA0 Module 3 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF3 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA0 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
2 CCF2 PCA0 Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA0 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
1 CCF1 PCA0 Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA0 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
0 CCF0 PCA0 Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt
is enabled, setting this bit causes the CPU to vector to the PCA0 interrupt service rou-
tine. This bit is not automatically cleared by hardware and must be cleared by software.
Rev. 1.2
325