C8051F58X Datasheet, PDF (20/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
C2CK/RST
VREGIN
VDD
GND
VDDA
GNDA
Power On
Reset
Reset
Debug /
Programming
Hardware
C2D
CIP-51 8051
Controller Core
128 or 96 kB Flash
Program Memory
256 Byte RAM
8 kB XRAM
Voltage Regulator
(LDO)
System Clock Setup
XTAL1 XTAL2
Internal Oscillator External Oscillator
Clock Multiplier
SFR
Bus
Port I/O Configuration
Digital Peripherals
UART0
UART1
Timers 0,
1,2,3,4,5
2x6
channel
PCA/WDT
LIN 2.1
CAN 2.0B
SPI
I2C
Priority
Crossbar
Decoder
Crossbar Control
External Memory Interface
*On F588, F590 devices
Analog Peripherals
Voltage
Reference _VREF
VDD
VREF
12-bit
200ksps
ADC
VDD
A VREF
M _{P0 – P3}
U
Temp
X
Sensor
GND
CP0, CP0A ₊
Comparator 0 ^-
CP2, CP2A ₊
-
Comparator 2
CP1, CP1A ₊
-
Comparator 1
Port 0
Drivers
Port 1
Drivers
Port 2
Drivers
Port 3
Drivers
Port 4
Driver
Figure 1.2. C8051F588/9-F590/1 Block Diagram
VIO
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0 / C2D
20
Rev. 1.2