C8051F58X Datasheet, PDF (336/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
29.3.2. Software Timer (Compare) Mode
In Software Timer mode, the PCA1 counter/timer value is compared to the module's 16-bit capture/com-
pare register (PCA1CPHn and PCA1CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in
PCA1CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module is
enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt ser-
vice routine, and must be cleared by software. Setting the ECOM1n and MAT1n bits in the PCA1CPMn
register enables Software Timer mode.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA1 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA1CPLn clears the
ECOM1n bit to 0; writing to PCA1CPHn sets ECOM1n to 1.
Write to
PCA1CPLn
0
ENB
Reset
Write to
PCA1CPHn ^ENB
1
PCA1CPMn
P ECCMT P E
WCA A AOWC
MOP P TGMC
1 MPN n 1 1 F
61111nn1
1nnn
n
n
x 00 00x
Enable
PCA1CPLn PCA1CPHn
16-bit Comparator
PCA1 Interrupt
Match
PCA1CN
CCCCCCCC
FRCCCCCC
11FFFFFF
119876
10
0
1
PCA1
Timebase
PCA1L
PCA1H
Figure 29.5. PCA1 Software Timer Mode Diagram
336
Rev. 1.2