C8051F58X Datasheet, PDF (191/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
Important Note on Crossbar Configuration: If a Port pin is claimed by a peripheral without use of the
Crossbar, its corresponding PnSKIP bit should be set. This applies to P0.0 if VREF is used, P0.1 if the
ADC is configured to use the external conversion start signal (CNVSTR), P0.3 and/or P0.2 if the external
oscillator circuit is enabled, and any selected ADC or Comparator inputs. The Crossbar skips selected pins
as if they were already assigned, and moves to the next unassigned pin.
Port
P0
P1
P2
P3
P4
Special
Function
Signals
P3.1-P3.7, P4.0 only P4.1-P4.7 only
available on the 48-pin available on the 48-
and 40-pin packages
pin packages
PIN I/O
0123456701234567012345670123456701234567
UART0_TX
UART0_RX
CAN_TX
CAN_RX
SCK
MISO
MOSI
NSS
SDA
SCL
CP0
CP0A
CP1
CP1A
SYSCLK
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
T0
T1
LIN_TX
LIN_RX
UART1_TX
UART1_RX
CP2
CP2A
CEX6
CEX7
CEX8
CEX9
CEX10
CEX11
ECI1
T4
T4EX
T5
T5EX
Figure 20.3. Peripheral Availability on Port I/O Pins
Registers XBR0, XBR1, XBR2, and XBR3 are used to assign the digital I/O resources to the physical I/O
Port pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the
SMBus (SDA and SCL); and similarly when the UART, CAN or LIN are selected, the Crossbar assigns both
pins associated with the peripheral (TX and RX).
Rev. 1.2
191