C8051F58X Datasheet, PDF (121/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
Table 13.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address
Description
FLSCL
0xB6
Flash Scale
IE
0xA8
Interrupt Enable
IP
0xB8
Interrupt Priority
IT01CF
0xE4
INT0/INT1 Configuration
LIN0ADR
0xD3
LIN0 Address
LIN0CF
0xC9
LIN0 Configuration
LIN0DAT
0xD2
LIN0 Data
OSCICN
0xA1
Internal Oscillator Control
OSCICRS
0xA2
Internal Oscillator Coarse Control
OSCIFIN
0x9E
Internal Oscillator Fine Calibration
OSCXCN
0x9F
External Oscillator Control
P0
0x80
Port 0 Latch
P0MASK
0xF2
Port 0 Mask Configuration
P0MAT
0xF1
Port 0 Match Configuration
P0MDIN
0xF1
Port 0 Input Mode Configuration
P0MDOUT
P0SKIP
P1
P1MASK
P1MAT
P1MDIN
P1MDOUT
0xA4
0xD4
0x90
0xF4
0xF3
0xF2
0xA5
Port 0 Output Mode Configuration
Port 0 Skip
Port 1 Latch
Port 1 Mask Configuration
Port 1 Match Configuration
Port 1 Input Mode Configuration
Port 1 Output Mode Configuration
P1SKIP
P2
P2MASK
P2MAT
P2MDIN
P2MDOUT
P2SKIP
P3
0xD5
0xA0
0xB2
0xB1
0xF3
0xA6
0xD6
0xB0
Port 1 Skip
Port 2 Latch
Port 2 Mask Configuration
Port 2 Match Configuration
Port 2 Input Mode Configuration
Port 2 Output Mode Configuration
Port 2 Skip
Port 3 Latch
P3MASK
P3MAT
P3MDIN
P3MDOUT
P3SKIP
P4
0xAF
0xAE
0xF4
0xAE
0xD7
0xB5
Port 3 Mask Configuration
Port 3 Match Configuration
Port 3 Input Mode Configuration
Port 3 Output Mode Configuration
Port 3 Skip
Port 4 Latch
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Rev. 1.2
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