C8051F58X Datasheet, PDF (186/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
20. Port Input/Output
Digital and analog resources are available through 40 (C8051F580/1/4/5), 33 (C8051F588/9-F590/1) or 25
(C8051F582/3/6/7) I/O pins. Port pins P0.0-P4.7 on the C8051F580/1/4/5, Port pins P0.0-P4.0 on the
C8051F588/9-F590/1 and Port pins P0.0-P3.0 on the C8051F582/3/6/7 can be defined as general-pur-
pose I/O (GPIO), assigned to one of the internal digital resources, or assigned to an analog function as
shown in Figure 20.3. Port pin P3.0 on the C8051F582/3/6/7 can be used as GPIO and is shared with the
C2 Interface Data signal (C2D). Port pin P4.0 on the C8051F588/9-F590/1 can be used as GPIO and is
shared with the C2 Interface Data signal (C2D) The designer has complete control over which functions
are assigned, limited only by the number of physical I/O pins. This resource assignment flexibility is
achieved through the use of a Priority Crossbar Decoder. Note that the state of a Port I/O pin can always
be read in the corresponding Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 20.3 and Figure 20.4). The registers XBR0, XBR1, XBR2, and XBR3 are used to select internal
digital functions. Port 4 on the C8051F580/1/4/5 and C8051F588/9-F590/1 is a digital-only port, which is
not assigned through the Crossbar.
All Port I/Os are 5 V tolerant (refer to Figure 20.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1). Complete
Electrical Specifications for Port I/O are given in Table 5.3 on page 47.
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