C8051F58X Datasheet, PDF (48/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
Table 5.4. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Parameter
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
Conditions
VIO = 5.0 V; IOL = 70 µA
Min
—
0.7 x V_IO
—
RST Input Pullup Current
RST = 0.0 V
—
V_DD POR Threshold (V_RST-LOW)
1.65
V_DD POR Threshold (V_RST-HIGH)
2.25
Time from last system clock
rising edge to reset initiation
Missing Clock Detector Timeout _{VDD = 2.1 V}
200
V_DD = 2.5 V
200
Reset Time Delay
Delay between release of
any reset source and code 
—
execution at location 0x0000
Minimum RST Low Time to 
Generate a System Reset
6
V_DD Monitor Turn-on Time
V_DD Monitor Supply Current
—
Typ
—
—
—
45
1.75
2.30
390
280
130
—
60
1
Max Units
40
mV
—
0.3 x V_IO
115
µA
1.80
V
2.45
V
µs
600
600
160
µs
—
µs
100
µs
2
µA
Table 5.5. Flash Electrical Characteristics
V_DD = 1.8 to 2.75 V, –40 to +125 °C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Flash Size
C8051F580/1/2/3/8/9
C8051F584/5/6/7-F590/1
131072^*
98304
Bytes
Endurance
20 k
150 k
—
Erase/Write
Flash Retention
85 °C
10
—
—
years
Erase Cycle Time
25 MHz System Clock
28
30
45
ms
Write Cycle Time
25 MHz System Clock
79
84
125
µs
V_DD
Write / Erase operations
V_RST-HIGH2
—
—
V
1. On the 128K Flash devices, 1024 bytes at addresses 0xFC00 to 0xFFFF (Bank 3) are reserved.
2. See Table 5.4 for the V_RST-HIGH specification.
48
Rev. 1.2