C8051F58X Datasheet, PDF (312/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
28. Programmable Counter Array 0 (PCA0)
The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU
intervention than the standard 8051 counter/timers. PCA0 consists of a dedicated 16-bit counter/timer and
six 16-bit capture/compare modules. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the Crossbar to Port I/O when enabled. The counter/timer is driven by a
programmable timebase that can select between eight sources: system clock, system clock divided by
four, system clock divided by twelve, the external oscillator clock source divided by 8, Timer 0, 4, or 5 over-
flows, or an external clock signal on the ECI input pin. Each capture/compare module may be configured to
operate independently in one of six modes: Edge-Triggered Capture, Software Timer, High-Speed Output,
Frequency Output, 8 to 11-Bit PWM, or 16-Bit PWM (each mode is described in Section
“28.3. Capture/Compare Modules” on page 315). The external oscillator clock option is ideal for real-time
clock (RTC) functionality, allowing PCA0 to be clocked by a precision external oscillator while the internal
oscillator drives the system clock. PCA0 is configured and controlled through the system controller's Spe-
cial Function Registers. The PCA0 block diagram is shown in Figure 28.1
Important Note: PCA0 Module 5 may be used as a watchdog timer (WDT), and is enabled in this mode
following a system reset. Access to certain PCA0 registers is restricted while WDT mode is enabled.
See Section 28.4 for details.
SYSCLK/12
SYSCLK/4
Timer 0 Overflow
ECI
SYSCLK
External Clock/8
Timer 4 Overflow
Timer 5 Overflow
PCA
CLOCK
MUX
16-Bit Counter/Timer
Capture/Compare
Module 0
Capture/Compare
Module 1
Capture/Compare
Module 2
Capture/Compare
Module 3
Capture/Compare
Module 4
Capture/Compare
Module 5 / WDT
Crossbar
Port I/O
Figure 28.1. PCA0 Block Diagram
312
Rev. 1.2