C8051F58X Datasheet, PDF (84/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
SFR Definition 9.6. CPT2MD: Comparator2 Mode Selection
Bit
7
6
5
4
3
2
1
0
Name
CP2RIE CP2FIE
CP2MD[1:0]
Type
R
R
R/W
R/W
R
R
R/W
Reset
0
0
0
0
0
0
1
0
SFR Address = 0x9B; SFR Page = 0x10
Bit
Name
Function
7:6 Unused Read = 00b, Write = Don’t Care.
5 CP2RIE Comparator2 Rising-Edge Interrupt Enable.
0: Comparator2 Rising-edge interrupt disabled.
1: Comparator2 Rising-edge interrupt enabled.
4
CP2FIE Comparator2 Falling-Edge Interrupt Enable.
0: Comparator2 Falling-edge interrupt disabled.
1: Comparator2 Falling-edge interrupt enabled.
3:2 Unused Read = 00b, Write = don’t care.
1:0 CP2MD[1:0] Comparator2 Mode Select.
These bits affect the response time and power consumption for Comparator2.
00: Mode 0 (Fastest Response Time, Highest Power Consumption)
01: Mode 1
10: Mode 2
11: Mode 3 (Slowest Response Time, Lowest Power Consumption)
84
Rev. 1.2