C8051F58X Datasheet, PDF (326/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
SFR Definition 28.2. PCA0MD: PCA0 Mode
Bit
7
6
5
4
Name ^CIDL
WDTE WDLCK
Type ^R/W
R/W
R/W
R
Reset
0
1
0
0
3
CPS2
R/W
0
2
CPS1
R/W
0
1
CPS0
R/W
0
0
ECF
R/W
0
SFR Address = 0xD9; SFR Page = 0x00
Bit Name
Function
7 CIDL PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
6 WDTE Watchdog Timer Enable
If this bit is set, PCA0 Module 5 is used as the watchdog timer.
0: Watchdog Timer disabled.
1: PCA0 Module 5 enabled as Watchdog Timer.
5 WDLCK Watchdog Timer Lock
This bit locks/unlocks the Watchdog Timer Enable. When WDLCK is set, the Watchdog
Timer may not be disabled until the next system reset.
0: Watchdog Timer Enable unlocked.
1: Watchdog Timer Enable locked.
4 Unused Read = 0b, Write = Don't care.
3:1 CPS[2:0] PCA0 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA0 counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
110: Timer 4 overflow
111: Timer 5 overflow
0
ECF PCA0 Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is
set.
Note: When the WDTE bit is set to 1, the other bits in the PCA0MD register cannot be modified. To change the
contents of the PCA0MD register, the Watchdog Timer must first be disabled.
326
Rev. 1.2