C8051F58X Datasheet, PDF (338/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
29.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA1 clocks to count before the
output is toggled. The frequency of the square wave is then defined by Equation 29.1.
F_CEXn = _2----------_P----_C-^F----_A^P---^C-1---^A-_C----_P-----_H----_n--
Note: A value of 0x00 in the PCA1CPHn register is equal to 256 for this equation.
Equation 29.1. Square Wave Frequency Output
Where F_PCA is the frequency of the clock selected by the CPS12–0 bits in the PCA1 mode register,
PCA1MD. The lower byte of the capture/compare module is compared to the PCA1 counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA1CPLn.
Frequency Output Mode is enabled by setting the ECOM1n, TOG1n, and PWM1n bits in the PCA1CPMn
register. Note that the MAT1n bit should normally be set to 0 in this mode. If the MAT1n bit is set to 1, the
CCFn flag for the channel will be set when the 16-bit PCA1 counter and the 16-bit capture/compare regis-
ter for the channel are equal.
Write to
PCA1CPLn
0
ENB
Reset
Write to
PCA1CPHn ^ENB
1
PCA1CPMn
P ECCMT P E
WCA A AOWC
MOPP TGMC
1 MPN n 1 1 F
61111nn1
1nnn
n
n
x 000
x
PCA1CPLn
Enable
8-bit
Comparator
8-bit Adder
PCA1CPHn
Adder
Enable
Toggle
match
TOG1n
0 _{CEXn Crossbar}
1
Port I/O
PCA1 Timebase
PCA1L
Figure 29.7. PCA1 Frequency Output Mode
338
Rev. 1.2