C8051F58X Datasheet, PDF (273/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
NSS
Master MISO
MOSI
Device 1
SCK
GPIO
GPIO
MISO _Master
MOSI
Device 2
SCK
NSS
Figure 26.2. Multiple-Master Mode Connection Diagram
Master
Device MISO
MOSI
SCK
Slave
MISO Device
MOSI
SCK
Figure 26.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram
Master
Device
GPIO
MISO
MOSI
SCK
NSS
MISO _Slave
MOSI _Device
SCK
NSS
MISO _Slave
MOSI _Device
SCK
NSS
Figure 26.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram
Rev. 1.2
273