C8051F58X Datasheet, PDF (187/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
Highest
Priority
UART0
2
2
CAN0
4
SPI0
2
SMBus0
4
CP0
2
CP1
/SYSCLK
7
PCA0
T0, T1,
4
/INT0,
/INT1
2
LIN0
Lowest
Priority
Port
Latches
2
UART1
2
CP2
7
PCA1
2
T4
2
T5
8x5
P0
P1
P2
(Px.0-Px.7)
P3 _{8 x 5}
P4
XBRn
PnSKIP
PnMDOUT,
PnDMIN Registers
Priority
Decoder
8
P0
I/O
Cells
Digital
Crossbar ₈
P1
I/O
Cells
External
Pins
P0.0 _Highest
Priority
P0.7
P1.0
P1.7
8
P2
P2.0
I/O
Cells
P2.7
8
P3
P3.0
I/O
Cells
P3.7
8
P4
I/O
Cells
P4.0
Lowest
P4.7 Priority
PnMASK
PnMATCH
Registers
Figure 20.1. Port I/O Functional Block Diagram
Rev. 1.2
187