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C8051F58X Datasheet, PDF (51/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current | |||
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C8051F58x/F59x
Table 5.9. ADC0 Electrical Characteristics
VDDA = 1.8 to 2.75 V, â40 to +125 °C, VREF = 1.5 V (REFSL=0) unless otherwise specified.
Parameter
Conditions
Min Typ
Max
Units
DC Accuracy
Resolution
12
bits
Integral Nonlinearity
â
±0.5
±3
LSB
Differential Nonlinearity
Guaranteed Monotonic
â
±0.5
±1
LSB
Offset Error1
â10 â1.6
10
LSB
Full Scale Error
â20 â4.2
20
LSB
Offset Temperature Coefficient
â
â2
â
ppm/°C
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
63
66
â
dB
Total Harmonic Distortion
Up to the 5th harmonic
â
81
â
dB
Spurious-Free Dynamic Range
â
â82
â
dB
Conversion Rate
SAR Conversion Clock
â
â
3.6
MHz
Conversion Time in SAR Clocks2
13
â
â
clocks
Track/Hold Acquisition Time3
VDDA >2.0 V
VDDA < 2.0 V
1.5
â
â
µs
3.5
Throughput Rate4
VDDA >2.0 V
â
â
200
ksps
Analog Inputs
ADC Input Voltage Range5
gain = 1.0 (default)
gain = n
0
â
VREF
V
0
VREF / n
Absolute Pin Voltage with respect
to GND
0
â
VIO
V
Sampling Capacitance
â
29
â
pF
Input Multiplexer Impedance
â
5
â
kï
Power Specifications
Power Supply Current ï
(VDDA supplied to ADC0)
Operating Mode, 200 ksps
â
1100 1500
µA
Burst Mode (Idle)
â
1100 1500
µA
Power-On Time
5
â
â
µs
Power Supply Rejection Ratio
â
â60
â
mV/V
Notes:
1. Represents one standard deviation from the mean. Offset and full-scale error can be removed through
calibration.
2. An additional 2 FCLK cycles are required to start and complete a conversion
3. Additional tracking time may be required depending on the output impedance connected to the ADC input.
See Section â6.2.1. Settling Time Requirementsâ on page 59
4. An increase in tracking time will decrease the ADC throughput.
5. See Section â6.3. Selectable Gainâ on page 60 for more information about the setting the gain.
Rev. 1.2
51
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