C8051F58X Datasheet, PDF (354/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
 Updated all specification TBDs
Clarified and corrected text throughout the document.
Revision 1.0 to Revision 1.1
 Updated “Ordering Information” on page 22 to include -A (Automotive) devices and automotive
qualification information.
 Updated supply current related specifications throughout “5. Electrical Characteristics” .
 Updated SFR Definition 8.1 to change VREF high setting to 2.20 V from 2.25 V.
 Updated Table 5.12 on page 53 and Figure 9.1 on Page 77 to indicate that Comparators are powered
from V_IO and not V_DDA.
 Updated the Gain Table in “Calculating the Gain Value” on page 60 to fix the ADC0GNH Value in the
last row.
 Updated Table 11.1 on page 94 with correct timing for all branch instructions, MOVC, and CPL A.
 Updated “Programming The Flash Memory” on page 138 to clarify behavior of 8-bit MOVX instructions
and when writing/erasing Flash.
 Updated SFR Definition 15.3 (FLSCL) to include FLEWT bit definition. This bit must be set before
writing or erasing Flash. Also updated Table 5.5 on page 48 to reflect new Flash Write and Erase
timing.
 Updated “17.7. Flash Error Reset” with an additional cause of a Flash Error reset.
 Updated “20.1. Port I/O Modes of Operation” to remove note regarding interfacing to voltages above
VIO.
 Updated “23. SMBus” to remove all hardware ACK features, including SMB0ADM and SMB0ADR
SFRs.
 Updated “24.3.2. Data Reception” to clarify UART receive FIFO behavior.
 Updated SFR Definition 24.1 (SCON0) to correct SFR Page to 0x00 from All Pages.
 Various formatting changes and corrections throughout the document.
Note: All items from the C8051F58x/59x Errata dated July 1, 2009 are incorporated into this data sheet.
Revision 1.1 to Revision 1.2
 Updated “1. System Overview” with a voltage range specification for the internal oscillator.
 Updated Table 5.6, “Internal High-Frequency Oscillator Electrical Characteristics,” on page 49 with new
conditions for the internal oscillator accuracy. The internal oscillator accuracy is dependent on the
operating voltage range.
 Updated “5. Electrical Characteristics” to remove the internal oscillator curve across temperature
diagram.
 Updated Figure 6.4 with new timing diagram when using CNVSTR pin.
 Updated SFR Definition 8.1 (REF0CN) with oscillator suspend requirement for ZTCEN.
 Fixed incorrect cross references in “9. Comparators” .
 Updated SFR Definition 10.1 (REG0CN) with a new definition for Bit 6. The bit 6 reset value is 1b and
must be written to 1b.
 Updated SFR Definition 12.1 (PSBANK) with correct reset value.
 Updated “16.3. Suspend Mode” with note regarding ZTCEN.
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Rev. 1.2