C8051F58X Datasheet, PDF (337/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
29.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA1 Counter and the module's 16-bit capture/compare register (PCA1CPHn and
PCA1CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA1CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared
by software. Setting the TOG1n, MAT1n, and ECOM1n bits in the PCA1CPMn register enables the High-
Speed Output mode. If ECOM1n is cleared, the associated pin will retain its state, and not toggle on the
next match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA1 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA1CPLn clears the
ECOM1n bit to 0; writing to PCA1CPHn sets ECOM1n to 1.
Write to
PCA1CPLn
0
ENB
Reset
Write to
PCA1CPHn ^ENB
1
PCA1CPMn
P ECCMT P E
WCA A AOWC
MOP P TGMC
1 MPN n 1 1 F
61111nn1
1nnn
n
n
x 00
0x
PCA1 Interrupt
PCA1CPLn PCA1CPHn
PCA1CN
CCCCCCCC
FRCCCCCC
11FFFFFF
119876
10
Enable
16-bit Comparator
PCA1
Timebase
PCA1L
PCA1H
Match
0
1
Toggle
TOG1n
0 _CEXn
1
Crossbar
Figure 29.6. PCA1 High-Speed Output Mode Diagram
Port I/O
Rev. 1.2
337