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C8051F58X Datasheet, PDF (282/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current
C8051F58x/F59x
Table 26.1. SPI Slave Timing Parameters
Parameter Description
Min
Max
Units
Master Mode Timing* (See Figure 26.8 and Figure 26.9)
TMCKH
TMCKL
SCK High Time
SCK Low Time
1 x TSYSCLK
1 x TSYSCLK
—
ns
—
ns
TMIS
MISO Valid to SCK Shift Edge
1 x TSYSCLK + 20
—
ns
TMIH
SCK Shift Edge to MISO Change
0
—
ns
Slave Mode Timing* (See Figure 26.10 and Figure 26.11)
TSE
NSS Falling to First SCK Edge
2 x TSYSCLK
—
ns
TSD
Last SCK Edge to NSS Rising
2 x TSYSCLK
—
ns
TSEZ
NSS Falling to MISO Valid
—
4 x TSYSCLK ns
TSDZ
NSS Rising to MISO High-Z
—
4 x TSYSCLK ns
TCKH
SCK High Time
5 x TSYSCLK
—
ns
TCKL
SCK Low Time
5 x TSYSCLK
—
ns
TSIS
MOSI Valid to SCK Sample Edge
2 x TSYSCLK
—
ns
TSIH
SCK Sample Edge to MOSI Change
2 x TSYSCLK
—
ns
TSOH
TSLH
SCK Shift Edge to MISO Change
Last SCK Edge to MISO Change 
(CKPHA = 1 ONLY)
—
6 x TSYSCLK
4 x TSYSCLK ns
8 x TSYSCLK ns
*Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
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Rev. 1.2