C8051F58X Datasheet, PDF (310/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
SFR Definition 27.20. TMRnCAPL: Timer 4 and 5 Capture Register Low Byte
Bit
7
6
5
4
3
2
1
0
Name
TMRnRLL[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
TMR4CAPL SFR Address = 0xCA; TMR5CAPL SFR Address = 0x92; SFR Page = 0x10
Bit
Name
Function
7:0 TMRnCAPL[7:0] Timer n Reload Register Low Byte.
TMRnCAPL captures the low byte of Timer 4 and 5 when Timer 4 and 5 are con-
figured in capture mode. When Timer 4 and 5 are configured in auto-reload
mode, it holds the low byte of the reload value.
SFR Definition 27.21. TMRnCAPH: Timer 4 and 5 Capture Register High Byte
Bit
7
6
5
4
3
2
1
0
Name
TMRnRLH[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
TMR4CAPH SFR Address = 0xCB; TMR5CAPH SFR Address = 0x93; SFR Page = 0x10
Bit
Name
Function
7:0 TMRnCAPH[7:0] Timer n Reload Register High Byte.
TMRnCAPH captures the high byte of Timer 4 and 5 when Timer 4 and 5 are
configured in capture mode. When Timer 4 and 5 are configured in auto-reload
mode, it holds the high byte of the reload value.
310
Rev. 1.2