C8051F58X Datasheet, PDF (201/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
SFR Definition 20.11. P3MASK: Port 3 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
P3MASK[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xAF; SFR Page = 0x00
Bit
Name
Function
7:0 P3MASK[7:0] Port 1 Mask Value.
Selects P3 pins to be compared to the corresponding bits in P3MAT.
0: P3.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P3.n pin logic value is compared to P3MAT.n.
Note: P3.1–P3.6 are only available on the 48-pin and 40-pin packages
SFR Definition 20.12. P3MAT: Port 3 Match Register
Bit
7
6
5
4
3
2
1
0
Name
P3MAT[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Address = 0xAE; SFR Page = 0x00
Bit
Name
Function
7:0 P3MAT[7:0] Port 3 Match Value.
Match comparison value used on Port 3 for bits in P3MAT which are set to 1.
0: P3.n pin logic value is compared with logic LOW.
1: P3.n pin logic value is compared with logic HIGH.
Note: P3.1–P3.6 are only available on the 48-pin and 40-pin packages
Rev. 1.2
201