C8051F58X Datasheet, PDF (266/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
Data transmission begins when an instruction writes a data byte to the SBUF1 register. The TI1 Transmit
Interrupt Flag (SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to 1. After the stop bit is
received, the data byte will be loaded into the SBUF1 receive register if the following conditions are met:
(1) RI1 must be logic 0, and (2) if MCE1 is logic 1, the 9th bit must be logic 1 (when MCE1 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF1, the ninth bit is stored in RB81, and the RI1 flag is set to 1. If the above conditions are not met,
SBUF1 and RB81 will not be loaded and the RI1 flag will not be set to 1. A UART1 interrupt will occur if
enabled when either TI1 or RI1 is set to ‘1’.
MARK
SPACE
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
STOP
BIT
BIT TIMES
BIT SAMPLING
Figure 25.5. 9-Bit UART Timing Diagram
25.3. Multiprocessor Communications
9-Bit UART mode supports multiprocessor communication between a master processor and one or more
slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or
more slaves, it first sends an address byte to select the target(s). An address byte differs from a data byte
in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0.
Setting the MCE1 bit (SCON1.5) of a slave processor configures its UART such that when a stop bit is
received, the UART will generate an interrupt only if the ninth bit is logic 1 (RB81 = 1) signifying an address
byte has been received. In the UART interrupt handler, software will compare the received address with
the slave's own assigned 8-bit address. If the addresses match, the slave will clear its MCE1 bit to enable
interrupts on the reception of the following data byte(s). Slaves that weren't addressed leave their MCE1
bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the
data. Once the entire message is received, the addressed slave resets its MCE1 bit to ignore all transmis-
sions until it receives the next address byte.
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The master
processor can be configured to receive all transmissions or a protocol can be implemented such that the
master/slave role is temporarily reversed to enable half-duplex transmission between the original master
and slave(s).
Master
Device
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
Slave
Device
V+
RX
TX
Figure 25.6. UART Multi-Processor Mode Interconnect Diagram
266
Rev. 1.2