C8051F58X Datasheet, PDF (344/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
SFR Definition 29.2. PCA1MD: PCA1 Mode
Bit
7
6
5
4
3
2
1
0
Name ^CIDL1
CPS12 CPS11 CPS10 ECF1
Type ^R/W
R
R/W
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Address = 0xD9; SFR Page = 0x10
Bit Name
Function
7 CIDL1 PCA1 Counter/Timer Idle Control.
Specifies PCA1 behavior when CPU is in Idle Mode.
0: PCA1 continues to function normally while the system controller is in Idle Mode.
1: PCA1 operation is suspended while the system controller is in Idle Mode.
6:4 Unused Read = 000b, Write = Don't care.
3:1 CPS1[2:0] PCA1 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA1 counter
000: System clock divided by 12
001: System clock divided by 4
010: Timer 0 overflow
011: High-to-low transitions on ECI (max rate = system clock divided by 4)
100: System clock
101: External clock divided by 8 (synchronized with the system clock)
110: Timer 4 overflow
111: Timer 5 overflow
0 EC1F PCA1 Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA1 Counter/Timer Overflow (CF1) interrupt.
0: Disable the CF1 interrupt.
1: Enable a PCA1 Counter/Timer Overflow interrupt request when CF1 (PCA1CN.7) is
set.
344
Rev. 1.2