C8051F58X Datasheet, PDF (335/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
29.3.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes PCA1 to capture the value of the PCA1 coun-
ter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA1CPLn and
PCA1CPHn). The CAPP1n and CAPN1n bits in the PCA1CPMn register are used to select the type of
transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative
edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag
(CCFn) in PCA1CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module
is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt
service routine, and must be cleared by software. If both CAPP1n and CAPN1n bits are set to logic 1, then
the state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or
falling-edge caused the capture.
PCA1CPMn
P ECCMT P E
WCA A AOWC
MOP P TGMC
1 MPN n 1 1 F
61111nn1
1nnn
n
n
xx
000x
PCA1 Interrupt
PCA1CN
CCCCCCCC
FRCCCCCC
11FFFFFF
119876
10
Port I/O
Crossbar ^CEXn
0
1
0
1
PCA1CPLn PCA1CPHn
Capture
PCA1
Timebase
PCA1L
PCA1H
Figure 29.4. PCA1 Capture Mode Diagram
Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the
hardware.
Rev. 1.2
335