C8051F58X Datasheet, PDF (324/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
The PCA0 clock source and Idle mode select cannot be changed while the WDT is enabled. The watchdog
timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL5 defaults to 0x00. Using Equation 28.5, this results in a WDT
timeout interval of 256 PCA0 clock cycles, or 3072 system clock cycles. Table 28.3 lists some example
timeout intervals for typical system clocks.
Table 28.3. Watchdog Timer Timeout Intervals¹
System Clock (Hz)
PCA0CPL5 Timeout Interval (ms)
24,000,000
255
24,000,000
128
24,000,000
32
3,000,000
255
3,000,000
128
3,000,000
32
187,500²
255
187,500²
128
187,500²
32
32.8
16.5
4.2
262.1
132.1
33.8
4194
2114
541
Notes:
1. Assumes SYSCLK/12 as the PCA0 clock source, and a PCA0L
value of 0x00 at the update time.
2. Internal SYSCLK reset frequency = Internal Oscillator divided by
128.
324
Rev. 1.2