C8051F58X Datasheet, PDF(323/356 Page) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

C8051F58X Datasheet, PDF (323/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

◁

C8051F58x/F59x

PCA0MD

CWW

I DD

DT L

LEC

K

CCCE

PPPC

SSSF

210

PCA0CPH5

8-bit

Enable Comparator

Match

Reset

PCA0CPL5

8-bit Adder

PCA0H

PCA0L Overflow

Write to

PCA0CPH2

Adder

Enable

Figure 28.11. PCA0 Module 5 with Watchdog Timer Enabled

Note that the 8-bit offset held in PCA0CPH5 is compared to the upper byte of the 16-bit PCA0 counter.

This offset value is the number of PCA0L overflows before a reset. Up to 256 PCA0 clocks may pass

before the first PCA0L overflow occurs, depending on the value of the PCA0L when the update is per-

formed. The total offset is then given (in PCA0 clocks) by Equation 28.5, where PCA0L is the value of the

PCA0L register at the time of the update.

Offset = ï¨256 x PCA0CPL5ï© + ï¨256 â PCA0Lï©

Equation 28.5. Watchdog Timer Offset in PCA0 Clocks

The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH5 and

PCA0H. Software may force a WDT reset by writing a 1 to the CCF5 flag (PCA0CN.5) while the WDT is

enabled.

28.4.2. Watchdog Timer Usage

To configure the WDT, perform the following tasks:

ï® Disable the WDT by writing a 0 to the WDTE bit.

ï® Select the desired PCA0 clock source (with the CPS2âCPS0 bits).

ï® Load PCA0CPL5 with the desired WDT update offset value.

ï® Configure the PCA0 Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle

mode).

ï® Enable the WDT by setting the WDTE bit to 1.

ï® Reset the WDT timer by writing to PCA0CPH5.

Rev. 1.2

323

▷