C8051F58X Datasheet, PDF (24/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F58x/F59x
Name
Pin
F580/1/4/5
(48-pin)
Pin
F588/9-
F590/1
(40-pin)
Pin
F582/3/6/7
(32-pin)
Type
VDD
4
4
4
GND
6
6
6
VDDA
5
5
5
GNDA
7
7
7
VREGIN
3
3
3
VIO
2
2
2
RST/
12
10
10 D I/O
Description
Digital Supply Voltage. Must be connected.
Digital Ground. Must be connected.
Analog Supply Voltage. Must be connected.
Analog Ground. Must be connected.
Voltage Regulator Input
Port I/O Supply Voltage. Must be connected.
Device Reset. Open-drain output of internal
POR or V_DD Monitor. An external source
can initiate a system reset by driving this pin
low.
C2CK
D I/O
Clock signal for the C2 Debug Interface.
C2D
11
—
— D I/O
Bi-directional data signal for the C2 Debug
Interface.
P4.0/
—
9
— D I/O or A In Port 4.0. See SFR Definition 20.29 for a
description.
C2D
P3.0/
—
D I/O
Bi-directional data signal for the C2 Debug
Interface.
9 D I/O or A In Port 3.0. See SFR Definition 20.25 for a
description.
C2D
D I/O
Bi-directional data signal for the C2 Debug
Interface.
P0.0
8
8
8 D I/O or A In Port 0.0. See SFR Definition 20.13 for a
description.
P0.1
1
1
1 D I/O or A In Port 0.1
P0.2
48
40
32 D I/O or A In Port 0.2
P0.3
47
39
31 D I/O or A In Port 0.3
P0.4
46
38
30 D I/O or A In Port 0.4
P0.5
45
37
29 D I/O or A In Port 0.5
24
Rev. 1.2