C8051F58X Datasheet, PDF (196/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
SFR Definition 20.3. XBR2: Port I/O Crossbar Register 2
Bit
7
Name ^WEAKPUD
Type
R/W
Reset
0
6
XBARE
R/W
0
5
4
Reserved
R/W
R/W
0
0
3
CP2AE
R/W
0
2
CP2E
R/W
0
1
URT1E
R/W
0
0
LIN0E
R/W
0
SFR Address = 0xC7; SFR Page = 0x0F
Bit
Name
Function
7 WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6
XBARE Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
5:4 Reserved Always Write to 00b.
3
CP2AE Comparator2 Asynchronous Output Enable.
0: Asynchronous CP2 unavailable at Port pin.
1: Asynchronous CP2 routed to Port pin.
2
CP2E Comparator2 Output Enable.
0: CP2 unavailable at Port pin.
1: CP2 routed to Port pin.
1
URT1E UART1 I/O Output Enable.
0: UART1 I/O unavailable at Port pin.
1: UART1 TX0, RX0 routed to Port pins.
0
LIN0E LIN I/O Output Enable.
0: LIN I/O unavailable at Port pin.
1: LIN_TX, LIN_RX routed to Port pins.
196
Rev. 1.2