C8051F58X Datasheet, PDF (54/356 Pages) Silicon Laboratories – Programmable hysteresis and response time Configurble as interrupt or reset source Low current

C8051F58x/F59x
6. 12-Bit ADC (ADC0)
The ADC0 on the C8051F58x/F59x consists of an analog multiplexer (AMUX0) with 35/28 total input selec-
tions and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-hold,
programmable window detector, programmable attenuation (1:2), and hardware accumulator. The ADC0
subsystem has a special Burst Mode which can automatically enable ADC0, capture and accumulate sam-
ples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0, data con-
version modes, and window detector are all configurable under software control via the Special Function
Registers shows in Figure 6.1. ADC0 inputs are single-ended and may be configured to measure P0.0-
P3.7, the Temperature Sensor output, V_DD, or GND with respect to GND. The voltage reference for ADC0
is selected as described in Section “7. Temperature Sensor” on page 74. ADC0 is enabled when the
AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in
Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are
taking place.
ADC0MX
ADC0TK
ADC0CN
*Available on 48-pin and
40-pin packages
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.1*
35-to-1
AMUX0
Start
Conversion
SYSCLK
Burst Mode
Logic
Burst Mode
Oscillator
25 MHz Max
Selectable
Gain
VDD
12-Bit
SAR
ADC
ADC0GNH ADC0GNL ADC0GNA
00
Start
Conversion
01
10
11
AD0BUSY (W)
Timer 1 Overflow
CNVSTR Input
Timer 2 Overflow
Accumulator
AD0WINT
P3.7*
VDD
Temp Sensor
GND
ADC0CF
ADC0LTH ADC0LTL
ADC0GTH ADC0GTL
Window
Compare
32 _Logic
Figure 6.1. ADC0 Functional Block Diagram
54
Rev. 1.2