JN517X Datasheet, PDF(98/100 Page) NXP Semiconductors

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JN517X Datasheet, PDF (98/100 Pages) NXP Semiconductors – Supports multiple network stacks

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NXP Semiconductors

JN517x

IEEE802.15.4 Wireless Microcontroller

25. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Fig 2. Functional block diagram . . . . . . . . . . . . . . . . . . . .6

Fig 3. Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . .7

Fig 4. Analog IO cell . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Fig 5. DIO (other than DIO4 and DIO5) pin equivalent

schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 6. DIO4 and DIO5 pin equivalent schematic . . . . . .14

Fig 7. JN517x memory map. . . . . . . . . . . . . . . . . . . . . .16

Fig 8. Connecting external serial memory . . . . . . . . . . .18

Fig 9. System and CPU clocks . . . . . . . . . . . . . . . . . . .19

Fig 10. 32 MHz crystal oscillator connections . . . . . . . . .20

Fig 11. 32 kHz crystal oscillator connections . . . . . . . . . .21

Fig 12. Internal Power-On Reset . . . . . . . . . . . . . . . . . . .22

Fig 13. External reset generation. . . . . . . . . . . . . . . . . . .23

Fig 14. External reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 15. Radio architecture . . . . . . . . . . . . . . . . . . . . . . . .26

Fig 16. External radio components . . . . . . . . . . . . . . . . .27

Fig 17. Simple antenna diversity implementation using

external RF switch . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 18. Antenna diversity ADO signal for TX with

acknowledgement . . . . . . . . . . . . . . . . . . . . . . . .29

Fig 19. Modem architecture . . . . . . . . . . . . . . . . . . . . . . .29

Fig 20. Energy detect value versus receive power level .30

Fig 21. Baseband processor . . . . . . . . . . . . . . . . . . . . . .31

Fig 22. Security coprocessor architecture . . . . . . . . . . . .32

Fig 23. SPI-bus block diagram. . . . . . . . . . . . . . . . . . . . .34

Fig 24. Typical JN517x SPI-bus peripheral connection . .35

Fig 25. Example SPI-bus waveforms: reading from

Flash device using mode 0 . . . . . . . . . . . . . . . . .37

Fig 26. Timer unit block diagram . . . . . . . . . . . . . . . . . . .39

Fig 27. PWM output timings. . . . . . . . . . . . . . . . . . . . . . .40

Fig 28. Capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Fig 29. Return-To-Zero mode in operation. . . . . . . . . . . .42

Fig 30. Non-Return-to-Zero mode . . . . . . . . . . . . . . . . . .42

Fig 31. Closed loop PWM speed control using JN517x

timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Fig 32. UART block diagram . . . . . . . . . . . . . . . . . . . . . .46

Fig 33. JN517x serial communication link . . . . . . . . . . . .48

Fig 34. Connection details . . . . . . . . . . . . . . . . . . . . . . . .50

Fig 35. Clock stretching . . . . . . . . . . . . . . . . . . . . . . . . . .50

Fig 36. TX_FIFO in the middle of a transaction . . . . . . . .51

Fig 37. RX_FIFO full in the middle of a transaction . . . . .52

Fig 38. TX_FIFO empty just before RESTART condition

in master slave case . . . . . . . . . . . . . . . . . . . . . .53

Fig 39. Slave receiver: RX_FIFO in middle

of a transaction . . . . . . . . . . . . . . . . . . . . . . . . . .54

Fig 40. Example of use of the SRSD interrupt

(STOP case) . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Fig 41. TXS_FIFO empty in the middle of a transaction .55

Fig 42. Example of use of the STSD interrupt

(RESTART case) . . . . . . . . . . . . . . . . . . . . . . . . .56

Fig 43. Analog peripherals . . . . . . . . . . . . . . . . . . . . . . . .57

Fig 44. ADC input equivalent circuit. . . . . . . . . . . . . . . . .58

Fig 45. Internal Power-On Reset without showing

Brown-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Fig 46. Externally applied reset . . . . . . . . . . . . . . . . . . . .67

Fig 47. Brown-Out Reset followed by Supply Voltage

Monitor trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Fig 48. SPI-bus master timing. . . . . . . . . . . . . . . . . . . . . 69

Fig 49. SPI-bus slave timing . . . . . . . . . . . . . . . . . . . . . . 70

Fig 50. I2C-bus interface timing. . . . . . . . . . . . . . . . . . . . 70

Fig 51. Typical control range output power . . . . . . . . . . . 80

Fig 52. Typical transmit output power versus voltage . . . 81

Fig 53. Typical receiver sensitivity versus temperature. . 81

Fig 54. Maximum input level . . . . . . . . . . . . . . . . . . . . . . 82

Fig 55. JN517x module reference design using

low voltage supply . . . . . . . . . . . . . . . . . . . . . . . . 83

Fig 56. Application diagram with Pi filter . . . . . . . . . . . . . 84

Fig 57. Reflow soldering information for the HVQFN40

package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Fig 58. Package outline SOT618-8 HVQFN40 . . . . . . . . 87

Fig 59. Temperature profiles for large and small

components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

JN517X

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2.0 â 8 November 2016

98 of 100

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