JN517X Datasheet, PDF (17/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
9.3.2 RAM
The JN517x devices contain 32 kB of high-speed RAM. It is primarily used to hold the
CPU Stack together with program variables and data. If necessary, the CPU can execute
code contained within the RAM (although it would normally just execute code directly from
the embedded Flash). Software can control the power supply to the RAM allowing the
contents to be maintained during a sleep period when other parts of the device are
unpowered, allowing a quicker resumption of processing once woken.
9.3.3 OTP configuration memory
The JN517x contains a quantity of One Time Programmable (OTP) memory as part of the
embedded Flash (Index Sector). This can be used to securely hold such things as a user
64-bit MAC address and a 128-bit AES security key. By default the 64-bit MAC address is
pre-programmed by NXP on supplied parts; however the pre-programmed value can be
overridden by customers providing their own MAC addresses. The user MAC address and
other data can be written to the OTP memory using the Flash programmer. Details on how
to obtain and install MAC addresses can be found in the dedicated Application Note. In
addition, 128 bits are available for customer use for storage of configuration or other
information.
For further information on how to program and use this facility, refer to Flash Programmer
User Guide JN-UG-3099 on the Wireless Connectivity area of the NXP web site Ref. 2.
9.3.4 EEPROM
The JN517x contains 4 kB of EEPROM. The guaranteed endurance of the memory is
100 000 write cycles with typical endurance of 1 million cycles, while the data retention is
guaranteed for at least 10 years. EEPROM endurance can be extended using the
Persistent Data Manager software which wear levels the EEPROM as data is written to it.
This is supplied in the NXP ZigBee SDK.
This non-volatile memory is primarily used to hold persistent data generated from such
things as the Network Stack software component (for example network topology, routing
tables). As the EEPROM holds its contents through sleep and reset events, this means
more stable operation and faster recovery is possible after outages.
The memory can be erased by a single or multiple pages of 64 bytes. It can be written to
in single or multiple bytes up to 64 bytes. For further details, refer to the JN517x
Integrated Peripherals API User Guide JN-UG-3118 on the Wireless Connectivity area of
the NXP web site Ref. 2.
9.3.5 External memory
An optional external serial non-volatile memory (for instance Flash or EEPROM) with a
SPI-bus interface may be used to provide additional storage for program code, such as a
new code image or further data for the device when external power is removed. The
memory can be connected to the SPI-bus master interface using select line SPISEL0 (see
Figure 8 for details).
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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