JN517X Datasheet, PDF (45/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
slower the value will be higher. For a calibration count of 9000, indicating that the RC
oscillator period is running at approximately 35 kHz, to time for a period of 2 seconds the
timer should be loaded with 71,111 ((10000/9000)  (32000  2)) rather than 64000.
9.11 Pulse counters
Two 16-bit counters are provided that can increment during all modes of operation
(including sleep). The first, PC0, increments from pulses received on DIO1 or DIO13. The
other pulse counter, PC1 operates from DIO5 or DIO14 depending upon the configuration.
This is enabled under software control. The pulses can be de-bounced using the 32 kHz
clock to guard against false counting on slow or noisy edges. Increments occur from a
configurable rising or falling edge on the respective DIO input.
Each counter has an associated 16-bit reference that is loaded by the user. An interrupt
(and wake-up event if asleep) may be generated when a counter reaches its
pre-configured reference value. The 2 counters may optionally be cascaded together to
provide a single 32-bit counter, linked to any of the four DIOs. The counters do not
saturate at 65535, but naturally roll-over to 0. Additionally, the pulse counting continues
when the reference value is reached without software interaction so that pulses are not
missed even if there is a long delay before an interrupt is serviced or during the wake-up
process.
The system can work with signals up to 100 kHz, with no debounce, or from 5.3 kHz to
1.7 kHz with debounce. When using debounce the 32 kHz clock must be active, so for
minimum sleep currents the debounce mode should not be used.
9.12 Serial communications
The JN517x has two Universal Asynchronous Receiver/Transmitter (UART) serial
communication interfaces. These provide similar operating features to the industry
standard 16550A device operating in FIFO mode. The interfaces perform serial-to-parallel
conversion on incoming serial data and parallel-to-serial conversion on outgoing data from
the CPU to external devices. In both directions, a configurable FIFO buffer (with a default
depth of 16-byte) allows the CPU to read and write multiple characters on each
transaction. This means that the CPU is freed from handling data on a
character-by-character basis, with the associated high processor overhead. The UARTs
have the following features:
• Emulates behavior of industry standard NS16450 and NS16550A UARTs
• Configurable transmit and receive FIFO buffers (with default depths of 16 bytes for
each), with direct access to fill levels of each. Adds/deletes standard start, stop and
parity bits to/from the serial data
• Independently controlled transmit, receive, status and data sent interrupts
• Optional modem flow control signals CTS and RTS on UART0
• Fully programmable data formats: baud rate, start, stop and parity settings
• False start-bit detection, parity, framing and FIFO overrun error detect and break
indication
• Internal diagnostic capabilities: loopback controls for communications link fault
isolation
• Flow control by software or automatically by hardware
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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