JN517X Datasheet, PDF (53/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
Figure 38.
6
SCL
TX_FIFO empty:
Master stretches
the clock
7
8
JN517x
IEEE802.15.4 Wireless Microcontroller
Slv_add byte 0x1xx
have been written to
TX_FIFO
Ack
SDA
Slave transmits
MTDR
interrupt out.
NAck
from Master (Slave aborts transfer)
RESTART condition.
aaa-015458
Fig 38. TX_FIFO empty just before RESTART condition in master slave case
The master transmitter has to stretch the clock between the 8^th and the 9^th pulse when
TX_FIFO is empty, since it does not know whether it should send a NAck (next byte that
is programmed contains a restart) or an Ack (next byte is a normal dummy data byte).
Although the clock is stretched in the Ack cycle until the next dummy byte is written into
the TX_FIFO, the current data can already be read from the RX_FIFO, since the data is
written into the RX_FIFO on the 8th clock pulse. This implies that data can be read from
a slave on a byte by byte basis even when the TX_FIFO is empty.
4. If a STOP has been produced, a new transaction can be initiated by jumping back to
step 1 of the master receiver or transmitter mode. Otherwise for the RESTART case,
the start bit has to be programmed together with the slave address of the next
transaction. The previous byte will then not be acknowledged and the restart
produced. The next action will be then step 2 of the master receiver or transmitter
mode, depending on the slave address direction bit. When the master loses
arbitration, the data already received in the RX_FIFO is invalid. To prevent new slave
I²C-bus data from being written into the RX_FIFO while it still contains this invalid
data, the RX_FIFO_block signal is set (bit 10 of I2C_Status register). When the
RX_FIFO is accessed as a slave receiver after it has lost arbitration (as a master) and
the RX_FIFO was not cleared (emptied) the clock will be stretched, until the RX_FIFO
has been emptied. See Section 9.14.4.1 for more information.
Table 11. I²C-bus RX_FIFO master receiver reading data example
Instruction code
Description
0x149
master issues a START + slave address 24h (read operation)
0x0xx
the presence of the 3 dummy bytes indicates that the master expects 3
data bytes from the slave
0x0xx
-
0x2xx
master issues a STOP
9.14.4 Slave interface
When operating as a slave, the first thing that needs to be done is to set the addressing
mode (either 10-bit or 7-bit).
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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