JN517X Datasheet, PDF (61/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
• Active processing mode
• Sleep mode
• Deep sleep mode
The variation in power consumption of the 3 modes is a result of having a series of power
domains within the chip that may be selectively powered ON or OFF.
10.1.1 Power domains
The JN517x has the following power domains:
• V_DD supply domain: supplies the wake-up timers and controller, DIO blocks,
Comparator, SVM and BOR together with the Fast RC, 32 kHz RC and crystal
oscillator. This domain is driven from the external supply (battery) and is always
powered. The wake-up timers and controller, and the 32 kHz RC and crystal oscillator
may be powered ON or OFF in sleep mode through software control.
• Digital logic domain: supplies the digital peripherals, CPU, Flash when in active
processing mode, baseband controller, modem and encryption processor. It is
powered OFF during sleep or deep sleep mode.
• RAM domain: supplies the RAM when in active processing mode. Also supplies the
RAM during sleep mode to retain the memory contents. It may be powered ON or
OFF for sleep mode through software control.
• Radio domain: supplies the radio interface, ADCs and temperature sensor. It is
powered during transmit and receive and when the analog peripherals are enabled. It
is controlled by the baseband processor and is powered OFF during sleep or deep
sleep mode.
The current consumption figures for the different modes of operation of the device is given
in Section 14.1.
10.2 Active processing mode
Active processing mode in the JN517x is where all of the application processing takes
place. By default, the CPU will execute at the selected clock speed executing application
firmware. All of the peripherals are available to the application, as are options to actively
enable or disable them to control power consumption; see specific peripheral sections for
details.
While in active processing mode there is the option to doze the CPU but keep the rest of
the chip active; this is particularly useful for radio transmit and receive operations, where
the CPU operation is not required therefore saving power.
10.2.1 CPU doze
While in doze mode, CPU operation is stopped but the chip remains powered and the
digital peripherals continue to run. Doze mode is entered through software and is
terminated by any interrupt request. Once the interrupt service routine has been executed,
normal program execution resumes. Doze mode uses more power than sleep and deep
sleep modes but requires less time to restart and can therefore be used as a low-power
alternative to an idle loop.
While in CPU doze, the CPU is not drawing current, therefore the total device current is
reduced.
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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