JN517X Datasheet, PDF (39/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
sw system single
reset reset shot
RESET
GENERATOR
interrupt
interrupt
enable
INTERRUPT
GENERATOR
TIMxCAP⁽¹⁾
CAPTURE
GENERATOR
FALL
RISE
-1
<
=
TIM0CK_GT
edge
select
SYSCLK
PRESCALER
(1) With x = 0 or 1.
Fig 26. Timer unit block diagram
EN
COUNTER
PWM/∆Σ
EN
DELTA SIGMA
PWM/∆Σ
>=
DQ
TIMxOUT⁽¹⁾
PWM/∆Σ
aaa-015450
The clock source for the Timer0/Timer1 unit is fed from the system clock, selected as
16 MHz or 32 MHz. This clock passes to a 5-bit prescaler where a value of 0 leaves the
clock unmodified and other values divide it by 2^{prescale value}. For example, a prescale value
of 2 applied to the 16 MHz system clock source results in a timer clock of 4 MHz.
The counter is optionally gated by a signal on the clock/gate input (TIM0CK_GT). If the
gate function is selected, then the counter is frozen when the clock/gate input is high.
An interrupt can be generated whenever the counter is equal to the value in either of the
High or Low registers.
The Analog Peripheral Timer is dedicated for timing the analog peripherals, e.g. ADC and
comparator. APT inputs and outputs do not come to device pins.
Table 7 details which DIO is used for Timer0 and the PWM depending upon the
configuration.
Table 7. Timer and PWM I/O
Signal
DIO assignment
Standard pins
TIM0CK_GT
DIO4
TIM0CAP
DIO2
TIM0OUT
DIO3
Alternative pins
DIO15
DIO5
DIO8
JN517X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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