JN517X Datasheet, PDF (55/100 Pages) NXP Semiconductors – Supports multiple network stacks

NXP Semiconductors
JN517x
IEEE802.15.4 Wireless Microcontroller
7
SCL
8
Ack
SRSD
interrupt
1
2
SRSD still pending
≥ stretch clock
8
Ack
empty
RX_FIFO
+ clear int
1
SDA
Master transmits
NoAck
from slave
STOP + START
Master sends
slave address + write bit
Fig 40. Example of use of the SRSD interrupt (STOP case)
Master transmits
Slave acknowledges
and takes over the SDA line
aaa-015460
9.14.4.2 Slave transmitter
The slave transmitter data must be written to the TXS_FIFO. Each data byte must be
acknowledged by the master to continue the transaction.
If the TXS_FIFO is empty (interrupt STDR -Int_Status register bit 8- set), the slave will
automatically stretch the clock of the previous byte (after acknowledge) until some new
byte is loaded in the TXS_FIFO. See Figure 41.
TX/TXS_FIFO empty:
slave stretches
the clock
7
8
Ack
SCL
one or several bytes
have been written to
the TX/TXS_FIFO
1
2
JN517X
Product data sheet
SDA
acknowledge
by master
STDR
interrupt out
slave transmits again
aaa-016452
Fig 41. TXS_FIFO empty in the middle of a transaction
A transaction is aborted only when the master does not acknowledge a data byte, after
which the slave releases the data line. A STOP or a RESTART is then issued by the
master.
After the slave has been addressed in transmitter mode, the TXS_FIFO must be emptied
before the device is addressed again. This is notified externally via interrupt STSD
(Int_Status register bit 3), set when the slave transmitter sees a STOP or a RESTART on
the bus. The TXS_FIFO is then automatically blocked (I2C_Status register bit 11 set) and
must be flushed by software before clearing the interrupt. This blocking mechanism is
used to prevent unwanted data from remaining in the TXS_FIFO after the STOP or
RESTART on the bus. If the slave is addressed again in transmitter mode and the
TXS_FIFO has not been flushed, the slave will stretch the clock after acknowledging its
address, until the TXS_FIFO is flushed and filled up again with correct new data.
All information provided in this document is subject to legal disclaimers.
Rev. 2.0 — 8 November 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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